The present invention relates to a Bi-CMOS logic circuit comprising a bipolar transistor device and a CMOS transistor device which are formed on the same substrate, and more particularly, to a Bi-CMOS logic circuit used in the form of a semiconductor logic circuit for operating a circuit of a large output-load, such as an LSI memory.
An example of a Bi-CMOS logic circuit as described above, is disclosed in Japanese Patent Disclosure (KOKAI) No. 59-254223, published on Feb. 9, 1984.
This Bi-CMOS logic circuit is characterized in that the supply of base current to a totem pole-type output buffer is controlled by a CMOS device. FIG. 1 shows the Bi-CMOS logic circuit which operates as an inverter. As is shown in this figure, the totem pole-type output buffer comprises pull-up NPN bipolar transistor Q1 and pull-down NPN bipolar transistor Q2. The base of transistor Q2 is coupled to the output terminal of a CMOS inverter consisting of P-type MOSFET Q3 and N-type MOSFET Q4. P-type MOSFET Q3 is used to supply a base current to bipolar transistor Q1 so that the logic circuit outputs data "1". N-type MOSFET Q4 is used to pull a base charge from bipolar transistor Q1 so that the logic circuit outputs data "0". The base of pull-down NPN bipolar transistor Q2 is connected to the source of N-type MOSFET Q5 which is turned on or off by the potential at the node of bipolar transistors Q1 and Q2.
When the input signal supplied to input terminal IN is at "0" level, the output potential of the CMOS inverter comprising MOSFETs Q3 and Q4 is at "1" level. In this case, transistor Q1 is on, as, therefore, is MOSFET Q5. As the input signal rises from "0" level to "1" level, MOSFET Q5 remains on. A base current is, therefore, supplied to transistor Q2 from an input stage. On the other hand, as the input signal falls from "1" level to "0" level, MOSFET Q5 also remains on. Hence, the base charge is pulled from transistor Q2 to the input stage.
The Bi-CMOS logic circuit has no DC paths, unlike a logic circuit comprising only bipolar transistors. Its power consumption is, therefore, as small as that of a CMOS logic circuit. Furthermore, since it has a current buffer composed of bipolar transistors, it can provide a greater drive-current than a logic circuit comprising only a CMOS device. For the same reason, it can operate at as high a speed as a bipolar logic circuit.
The Bi-CMOS logic circuit shown in FIG. 1 is, however, disadvantageous in the following respect:
When the gate-source voltage of N-type MOSFET Q5 falls below its threshold voltage V.sub.T (about 1 V), during the operation in which the output signal of "0" level is generated, transistor Q5 is inevitably turned off. Consequently, the output potential cannot fall below V.sub.T +V.sub.F, where VF is the base-emitter voltage of transistor Q2 and is usually about 0.7 V. Hence, when the Bi-CMOS logic circuit drives a CMOS logic circuit, the "0" output level can be higher, in some cases, than the gate threshold voltage of the next-stage N-type MOSFET. In such a case, the current component flowing from the power supply terminal of the CMOS logic circuit to the ground thereof will increase, resulting in considerable power consumption in the CMOS logic circuit.